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Best-in-Test 2014 finalists: Software/Embedded test

Best-in-Test 2014 finalists: Software/Embedded test


Very soon we will get to know who has managed to win Best-in-Test Award annually held to announce innovative developments worthy to become the best in test and measuring world. Winners will be rewarded on January 29 in Santa Clara Convention Center, Santa Clara, CA, USA.

Here are the winners in category Software/Embedded test.

x1149 Boundary Scan Analyzer, Agilent Technologies

Boundary scan has become an indispensable technology as engineers face increasing test access challenges. The x1149 boundary scan analyzer is a versatile yet easy to use board test tool. Unlike conventional benchtop boundary scan tools, the x1149 is designed to help users through board design and validation, and re-using the same x1149 test in manufacturing. This extends the return on invested capital for end-users and helps to save time and effort.

Offering an intuitive interface, the analyzer makes all information easily available on the screen with one mouse click.

Key features include:

  • Cover-Extend Technology and Silicon Nails capability.
  • STAPL player for CPLD/FPGA tests.
  • Scan Path Linker to link multiple chains into a single chain.
  • Fully compliant device support for IEEE 1149.1 and IEEE 1149.6 standard.

Agilent Technologies

ScanWorks Arium Real-Time Instruction Trace (RTIT) Debugger for Intel Silvermont, ASSET InterTech

The ScanWorks Arium SourcePoint debugger is one of the first to support Intel’s new Silvermont microarchitecture with its Real-Time Instruction Trace (RTIT) capabilities. For software engineers debugging code for multicore systems-on-a-chip (SoC) based on the Silvermont microarchitecture, the SourcePoint debugger is able to extend its debug and trace capabilities over the entire SoC. The instruction capture and display features of SourcePoint make the process much more intuitive because of the various views the developer has into code execution. For example, four different types of views—code, trace, branch and chart—give developers the ability to easily visualize code execution even when code is running on multiple cores. All four views are synchronized to simplify moving from one view to another. The root causes of bugs like performance bottlenecks or execution ordering problems can be quickly visualized for further analysis by the software developer. In addition, timestamps accurate to a particular processor cycle are provided by SourcePoint.

ASSET InterTech

ChipVORX for Bit Error Rate Tests, Goepel Electronic

The IP based ChipVORX technology now porvides the execution of Bit Error Rate (BER) tests. The highly automated solution enables FPGA Embedded Instruments utilization in the form of special softcores for the test and design validation of high-speed I/O. Users can now evaluate the transmission channel quality via BER measurements and an eye diagram.

ChipVORX controls the complete process flow starting with Target FPGA programming, IP to pin configuration, instrument control, and data processing and the final IP unloading. In the debug mode, the BERT parameters can be changed interactively for immediate effect without design synthesis. That makes the utilization of the new BERT solution highly efficient and user-friendly.

(BER) tests let engineers evaluate the channel quality in digital transmission systems. The equipment consists basically of the pattern generator, a transceiver with error detector, and a clock generator. The bit patterns, created by the pattern generator, have critical influence on the fault stimulation during the transmission (stress pattern).

ChipVORX is an IP-based technology for implementation, access and control of Chip embedded Instruments via IEEE Std. 1149.x/JTAG. It also supports FPGA embedded instruments in the form of softcores. The ChipVORX library currently contains more than 300 different test and measurement instruments for all leading FPGA platforms. Some of these instruments are frequency meters and high-speed Flash programmers as well as IP for at-speed access test of dynamic RAM devices.

GOEPEL Electronic

ATEasy Test Executive and Development Studio 9.0, Marvin Test Solutions

ATEasy 9.0 serves both as a COTS stand-alone product as well as a key building block to MTS’s vertically-integrated solutions for aerospace test and measurement applications.

ATEasy is designed for the development and maintenance of functional test applications. Its open architecture supports a range of software and hardware tools and standards, including .NET, ActiveX/COM, .DLL, IVI, Function Panel drivers, and NI LabVIEW.

With ATEasy 9.0, users can:

  • Take advantage of comprehensive hardware and software simulation that allows them to develop, run, debug, and analyze applications on a desktop with partial or no hardware. They can also simulate any existing driver, system, program, or UUT response with no source code changes required in order to support simulation.
  • Use ATEasy 9.0 development environment and run-time with a previous ATEasy version simultaneously, simplifying the version upgrade process and test program migration.
  • Integrate various third-party source and version control tools, such as Microsoft Team Foundation Server and Source Safe, Subversion, Git, CVS, and others.
  • Benefit from new test development features, including Unicode support, Find All and Replace All improvements, support for multiple object selection and operations, path variables, automatic variable type and name prefix, enable/disable breakpoints, Shmoo plots, and more.

Marvin Test Solution

Tessent Hybrid TestKompress/LogicBIST Solution, Mentor Graphics

The Tessent Hybrid TestKompress/LogicBIST Solution combines the two test strategies used to test virtually all IC logic&emdash;automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). The technology was developed for the test challenges of ICs that require high-reliability low DPM (defect per million) manufacturing test, and an in-system test capability that is used when the system is in service. Until now, these two test methods required separate test logic and development efforts. Mentor’s Hybrid TK/LBIST innovation enables true hybrid test by generating unique test circuitry that can serve both functions, while integrating the test development flow.

A hybrid test methodology improves tester memory utilization during manufacturing test by using BIST’s pseudo-random patterns first to cover the faults that are easier to detect. Because stored patterns are no longer needed for these faults, additional tester pattern storage becomes available for compressed ATPG patterns that target the remaining, more difficult to detect, faults. Because each logic block is equipped with its own hybrid test infrastructure, it can be tested independently of other cores.

The hybrid’s logic BIST can be combined with other common BIST capabilities, like memory BIST, to provide in-system test coverage for most, if not all, of the design. This is essential for meeting reliability goals related to the new ISO 26262 automotive standard.

Mentor Graphics

Manchester and NRZ Configurable Decode, Teledyne LeCroy

Many of today's data-communication protocols are built on Manchester or NRZ (non-return-to-zero) encoding. In many cases, basic Manchester and NRZ schemes are modified to create more complex, specialized protocols. Designers are developing and debugging systems with these protocols and looking for bus analysis tools to simplify the process.

The Manchester and NRZ configurable decoders are the industry's first configurable protocol decoders for a wide range of oscilloscope platforms. The decoders enable users to specify a broad range of physical layer characteristics for Manchester-encoded or NRZ-encoded signals. The decoders define the grouping of bits into words, and words into frames, which makes short work of analysis for custom and/or proprietary protocols based on those generic encoding schemes. Decoded information is then shown in a color-coded overlay directly on top of the physical layer waveform.

Users may specify bit rates from 10bps to 10Gbps. Idle states, sync bits, header and footer information can all be configured to decode custom preambles or CRC details. Decoding is highly flexible: data mode can be in bits or words; viewing in hex, ASCII, or decimal; and bit order may be either LSB or MSB. Decoded information is displayed with a color-coded overlay which expands or contracts as the user adjusts the oscilloscope timebase or zooms in on the waveform for more details.

Teledyne LeCroy

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KIPiS 2017 #3
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