Speed up your design verification process with frequency domain clock jitter analysis
The demand for clock jitter analysis has increased as data rates have increased. In high-speed serial data links clock jitter affects data jitter at the transmitter, in the transmission line, and at the receiver. Measurements of clock quality assurance have also evolved. The emphasis is now on directly relating clock performance to system performance in terms of the Bit Error Ratio. We will review the role of reference clock and the effects of clock jitter on data jitter, and discuss a new measurement technique equipped with the Agilent E5001A Precision Clock Jitter Analysis Application running on the E5052B Signal Source Analyzer (SSA) that delivers unprecedented capabilities, ultra-low random jitter (RJ) measurement and real-time jitter spectrum analysis on both RJ and periodic jitter (PJ) components, allowing you to improve your design quality. We will also discuss the real-time measurement capability of the new solution that speeds up your design verification process.
The role of reference clock in the high-speed serial application
Figure 1 shows the reference clock major components. The transmitter usually serializes a set of lower rate parallel signals into a serial data stream. The transmission channel through which the signal propagates is a combination of backplanes and cables. The receiver interprets incoming serial data, re-clocks it and, usually, de-serializes it back into a parallel data stream. In many descriptions like this, the reference clock is considered more of a constituent than a key player, but, in high rate serial data systems we have to call the reference clock out as a key component. Typically the reference clock oscillates at a rate much lower than the data rate and is multiplied up in the transmitter. The transmitter uses the reference clock to define the timing of logic transitions in the serial data stream. The character of the reference clock is included in the data transmitted. At the receiver, two different things can happen. If the reference clock is not distributed, then the receiver recovers a clock from the data stream – using, for example, a Phase Locked Loop (PLL) – and uses that clock to position the sampling point in time. If the reference clock is distributed, then the receiver uses both the data signal and the reference clock to position the sampling point.
Figure 1. Role of the reference clock
Effects of clock jitter on data jitter from the transmitter
The reference clock is the ultimate source of system timing. It provides the time-base for the transmitter and, in both distributed and undistributed clock systems, the character of the reference clock is reproduced in the clock recovery circuit at the receiver. Now, we’ll examine how the clock-jitter is propagated in the transmitter of the system.
To define the timing of logic transitions, the transmitter must multiply the reference clock by an appropriate factor to get the data rate. For example, for a 100 MHz reference clock and a 5 Gb/s output signal, the transmitter would use a PLL to multiply the reference clock by a factor of fifty. The PLL multiplier both amplifies the jitter on the clock and introduces its own jitter, primarily RJ from the PLL Voltage Controlled Oscillator (VCO).The effect of frequency multiplication by a factor of n is to multiply the phase noise power to carrier ratio by n2, so the jitter goes up fast.
Figure 2. Effect of clock jitter on transmitter
The PLL multiplier in the transmitter has a certain frequency response, typically a second order response like shown in Figure 3. The non-uniform frequency response raises an interesting question: What clock-jitter actually matters? If the PLL were perfect and had zero bandwidth, then it would filter out all the clock-jitter and provide the transmitter with a jitter-free time-base. Of course, zero bandwidth means infinite lock time, so we have to compromise, but the narrower the PLL bandwidth, the less jitter from the reference clock makes it into the data. Determining whether or not a clock will function in a system at the desired BER requires careful testing of the jitter frequency spectrum.
Figure 3. PLL frequency response
Jitter sources in the real world
If you look at a high speed digital circuit in the real world, there are many jitter sources as shown in Figure 4. As we reviewed previously, clock signal is often distributed to multiple ICs and clock frequency may be multiplied and/or divided. Assuming that the reference clock coming from a crystal oscillator has even low jitter, the output clock multiplied or divided may be not clean due to the additive noise of ICs or interference from other devices.
One of the major contamination sources is the noise coming from switching power supply noise whose switching frequency is typically from 100 kHz to 1 MHz. The switching power supply noise may be injected to the clock signal line and it is observed as PJ shown in the left bottom graph.
Other periodic jitter component sources may be interferences from the data or clock lines and inter-modulation products may fall into the clock line, which is also observed as PJ components. As long as PJ components appear at far away from the clock frequency, it is practically possible to insert a band pass filter (or a low pass filter) in order to suppress them. However, the problem is when a periodic jitter falls close to clock frequency, because high-Q filter at high frequency is hardly available. Also for RJ of the reference clock, a clock divider can add broadband noise resulting RJ of the output clock signal may be increased.
For diagnosing problems, it is very important for designers to characterize clock jitter on the physically layout of the circuit and/or under the operating conditions.
Figure 4. Jitter sources in the real world
Characterizing clock jitter through phase noise measurement technique
Thorough analysis of a clock signal requires femto second accuracy which can only be achieved by a phase noise measurement technique. Phase noise analysis provides two key measurements, Sφ (fφ) and φ(t), which harbor all the phase information of the clock up to the limit of the phase noise measurement bandwidth.
Two important goals can be achieved by analyzing RJ on a phase noise analyzer. First, by integrating the RJ spectrum, the width of the corresponding RJ Gaussian distribution is extracted within the bandwidth of interest. Second, the major causes of RJ can be isolated by analyzing the power-series behavior of Sφ (fφ). (Figure 5)
PJ components are observed spurs in the phase noise spectrum. Knowledge of the PJ frequencies is helpful in diagnosing problems. Referring a PJ rms of each PJ frequency will also help you understand the contribution of each PJ component to the total clock jitter, to examine what if the total jitter becomes if a major PJ component would be removed. (Figure 6)
Figure 5. Analyzing RJ on phase noise measurement
Figure 6. PJ frequencies on phase noise measurement
Real-time jitter measurement by the advanced architecture
Unlike the traditional jitter measurement paradigm, the E5052B SSA with the E5001A software offers real-time jitter analysis on phase noise measurement. The instrument employs PLL with reference source method. It automatically detects a clock frequency and built-in reference source is automatically tuned to the clock frequency in a few millisecond, and measures noise signal coming out of the phase detector maintaining PLL. The noise signals are captured at 250 MSa/s ADC enabling up to 100 MHz jitter bandwidth measurement which covers OC-192 jitter analysis range. Real time FFT is to obtain frequency domain data dramatically improves the speed of the measurement. As an example, it takes only 0.3 second per measurement from 1 kHz to 100 MHz bandwidth.
Figure 7. Advanced architecture of Agilent E5052B Signal Source Analyzer
Unprecedented jitter noise floor with cross-correlation technique
The E5052B jitter-measurement resolution and noise floor are exceptionally low, typically on the order of a few femto-seconds of RJ noise-floor at a 10Gbps rate. The typical high-performance (real-time or sampling) oscilloscope has a jitter noise-floor above one hundred femto-seconds due to the limited dynamic-range of the ADC and relatively large residual jitter of its internal reference time base. The E5052B maintains wide dynamic-range by detecting phase-noise at baseband where a large carrier signal is cancelled out. The E5052B can extend the jitter measurement limit even below the residual jitter of its internal time base by using a unique cross-correlation technique between two independent internal measurement channels. (See Figure 7) Using this cross-correlation technique, the E5052B achieves 100 times to 1,000 times lower jitter noise floor when compared to today’s high performance oscilloscope.
Figure 8. Ultimate jitter noise floor with cross-correlation technique
Emulate the PLL response in real-time
Figure 9 is an example of the effect of a PLL response function applied directly to the phase noise signal of a clock. You can see how different parts of the spectra are suppressed which allows for analysis of the jitter that is relevant to the application. The E5052B’s real-time jitter analysis on phase noise measurement speeds up your design process. Any PLL response functions can be imported to the E5052B SSA and you can emulate the PLL response from device to device very easily and quickly.
Figure 9. Emulate PLL response
For high speed serial data applications the primary goal of clock-jitter analysis is to determine the effect that the jitter of the reference clock has on the bit error ratio of the system. The most accurate approach is to apply the transfer functions of the worst case transmitter (and receiver) for the application to the clock and measure the resulting clock RJ and PJ. The E5001A Precision Clock Jitter Analysis software running on the E5052B changes traditional jitter measurement paradigm, not only offers thorough analysis of your clock jitter with a femto second resolution, but also the ease-of-use and real-time jitter analysis capability helping you speed up the design verification process.
Author(s): Akihiko Oginuma
Issue: KIPiS 2008 #4
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