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Best-in-Test 2014 finalists: Semiconductor Test

Best-in-Test 2014 finalists: Semiconductor Test


Very soon we will get to know who has managed to win Best-in-Test Award annually held to announce innovative developments worthy to become the best in test and measuring world. Winners will be rewarded on January 29 in Santa Clara Convention Center, Santa Clara, CA, USA.

Here are the winners in category Semiconductor Test.

CM300 Probe System, Cascade Microtech

The CM300 is an on-wafer measurement system, scalable from semi-automated to fully-automated prober or cluster probe system. The CM300 automates on-wafer device measurements and enhances device and process characterization and modeling by capturing the true electrical performance of devices and enabling hands-off productivity.

With fast and well-characterized thermal transition and probe-to-pad alignment, the CM300 processes a high volume of measurement data with accuracy on pads as small as 30µm. The CM300’s measurement automation, including the ability to reduce idle time while testing over a wide span of temperatures, and test automation using the Velox probe station control software, improves throughput while delivering high volumes of reliable data. With Velox software, the CM300 enables safe and fast wafer loading and easy test automation and measurement system integration, while preventing damage of probe tips, probe cards and customer wafers throughout the entire measurement cycle.

Cascade Microtech partnered with imec to successfully probe 25µm-diameter micro-bumps on a wide I/O test wafer with the fully-automated CM300 platform and advance Pyramid Probe technology. This achievement comes as part of imec’s 3D integration research program which includes other industry partners from the entire semiconductor value chain. The CM300 has proven to meet the fine-pitch (40µm area array), low-force (<1gf/tip) advanced probing requirements of 3D-SICs.

Cascade Microtech

Nighthawk RF Connectivity IC Tester, LTX-Credence

Connectivity semiconductors are high volume, price sensitive ICs used in many consumer products. Future growth challenges include ever increasing performance requirements and competitive margin pressure.

Sometimes, the only option is to stretch legacy test systems into massive multi-site configurations. Nighthawk, the result of 30 years of RF/DSP test experience, improves on every aspect of production test and cost.

Nighthawk’s leverages the same RF semiconductor innovations that enable today’s consumer connectivity solutions. It matches the ever shrinking semiconductor ASP with a high performance, low-priced RF test system. Nighthawk embeds all required source, measure, and DSP modules into a small air-cooled package that only reduces the cost of the RF system and replaces expensive test instrumentation. Nighthawk provides true quad-site parallel transceiver test capability at a fraction of the cost of traditional test systems.

Nighthawk features:

  • Dynamic Range Enhancement (DRE) provides over 120dB of dynamic range enhancement enabling accurate measurements under low and noisy input conditions
  • 2ms frequency and amplitude settling assures optimum production throughput
  • Wide analog bandwidth digitizer provides for accurate, single capture testing of all communication standards

Nighthawk can directly source, measure and decode a wide variety of baseband schemes.

Test time is enhanced by a powerful parallel processing FPGA providing real time Decimation and Dynamic Range Enhancement (DRE). Each of the 4 IF/Baseband digitizers are backed with extensive "test any device" 16Msample capture memory.


DFTMAX Ultra Compression Architecture, Synopsys

DFTMAX Ultra is improving test quality and lowering test cost. It is a comprehensive synthesis-based architecture for compression and advanced design-for-test that addresses the most demanding test quality and test cost requirements.

DFTMAX Ultra delivers 2-3X higher compression than previous technology to address the more demanding test application time/test data volume reduction (TATR/TDVR) requirements of large SoCs and high defect-coverage testing. It accomplishes this using a bidirectional compressor/decompressor (codec) that enables simultaneous streaming and de/compression of test data, thereby eliminating delays between scan shifts that occur in standard serial-deserialization implementations. The architecture also provides Synopsys’ TetraMAX ATPG with maximum flexibility to target faults and manage unknown logic values.

Test application time can be further reduced by scanning test data in and out of designs faster, using a higher tester clock frequency to increase the rate that internal scan chains are shifted. Pipelined processing of all data in and out of the DFTMAX Ultra codec facilitates high-speed shifting of the test data, making it possible to utilize the maximum performance of tester equipment to further reduce test application time and cost by a factor of 4-6X.

The DFTMAX Ultra produces higher defect coverage and 20X or more reduction in manufacturing test costs. For superior quality of results and faster turnaround time, design teams use DFTMAX Ultra together with the Synopsys Galaxy Implementation Platform suite of tools, concurrently optimizing and performing intelligent tradeoffs between speed, area, power, test and yield.


DesignWare STAR Hierarchical System, Synopsys

The DesignWare STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. The STAR Hierarchical System addresses increasing productivity and low-cost test requirements as SoC test becomes more complex as a result of larger designs and more extensive use of IP.

The STAR Hierarchical System reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level. That provides easy integration of the SoC test resources, allowing global design teams working on different areas of the SoC.

The system also reduces test cost and increases test quality. The STAR Hierarchical System gives designers the flexibility to schedule individual IP/cores for parallel or serial testing to optimize test time and power consumption during test.

The system also simplifies SoC test pattern creation and silicon debug using the IEEE 1500 network to port IP- or core-level patterns to the SoC level, and enabling the IP debug test modes from the SoC level. It helps improve SoC yield by enabling eFUSE programming for calibration and trimming of analog/mixed-signal IP.

The system’s design-for-test (DFT) implementation and hierarchical IP and core-level test lets engineering teams to cut their test integration time and bring their designs to market faster, with lower design and test costs.


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